1. Field of the Invention
The present invention relates to ultra low dielectric constant (ULK) and air gap-containing metal-insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) devices and packaging. More particularly, the present invention relates to structures, methods, and materials relating to the incorporation of ULK materials and air gaps into multiple levels of multilayer interconnect structures.
2. Description of the Prior Art
Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips typically have multilevel structures containing patterns of metal wiring layers that are encapsulated in an insulator. Wiring structures within a given level of wiring are separated by an intralevel dielectric, whereas the individual wiring levels are separated from each other by layers of an interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces.
Through their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed and thereby chip performance. Signal-propagation delays are due to RC time constants wherein “R” is the resistance of the on-chip wiring, and “C” is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants, k.
A preferred metal/dielectric combination for low RC interconnect structures is copper metal with a dielectric such as SiO2 (k˜4.0). Due to difficulties in subtractively patterning copper, copper-containing interconnect structures are typically fabricated by a damascene process. In a typical damascene process, metal patterns that are inset in a layer of dielectric are formed by the steps of: (i) etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel dielectric; (ii) optionally, lining the holes or trenches with one or more adhesion or diffusion barrier layers; (iii) overfilling the holes or trenches with a metal wiring material; and (iv) removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric.
The above-mentioned processing steps can be repeated until the desired number of wiring and via levels have been fabricated.
Fabrication of interconnect structures by damascene processing can be substantially simplified by using a process variation known as dual damascene (DD), in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. Dual damascene reduces the number of metal polishing steps by a factor of two, providing substantial cost savings, but requires that a dual-relief pattern be introduced into the combined via and wiring level dielectric.
A typical dual damascene process flow by methods of the prior art is shown in FIG. 1.
Examples of multilayer interconnect structures incorporating air gaps are described, for example, in U.S. Pat. No. 5,461,003 (Havemann et al.); U.S. Pat. No. 5,869,880 (Grill et al.); and U.S. Pat. No. 5,559,055 (Chang et al.).
A preferred prior art method for forming air gaps utilizes a sacrificial place-holder (SPH) material which is removed or extracted from beneath a solid or semi-permeable bridge layer. Examples of SPH materials and removal methods include poly (methylmethacrylate) (PMMA), poly-para-xylylene (Parylene™), amorphous carbon, and polystyrene, which may be removed by organic solvents, oxygen ashing, and/or low temperature (˜200° C.) oxidation, and norbornene-based materials such as BF Goodrich's Unity Sacrificial Polymer™, which may be removed by moderate temperature (350° C.-400° C.) thermal decomposition into volatiles.
In the case of the Unity material, the volatile decomposition by-product actually diffuses through the bridge layer, as demonstrated by Kohl et al., in Electrochemical and Solid-State Letters, 1, 49 (1998) for structures including partially porous SiO2 (500 nm) bridge layers deposited by a low temperature plasma enhanced chemical vapor deposition (PECVD) process.
However, in all these cases, the removal process, be it by a plasma based or a wet chemical process, or by thermal means, the SPH material or its decomposition or reaction products are required to diffuse through the semi-permeable bridge layer. This is generally very difficult to reduce to practice. If extraction is performed without a bridge layer being present in the structure as a means of bypassing this difficulty of extracting layers through a semi-permeable medium, it would be very difficult to place a bridge layer on top of the extracted structure.
Another concern with air gap based dielectric structures compared to structures with solid dielectrics is that air-gap based structures have lower thermal conductivity, reduced strength, and higher permeability to moisture and oxygen. Accordingly, any workable scheme for incorporating air gaps into interconnect structures must take these limitations into account.
A further concern with air gap dielectrics is that they leave metal wiring features more susceptible to the opens and shorts induced by electromigration-driven mass transport, since the wiring features are no longer physically constrained by being embedded in a solid dielectric.
Still another concern is that structures with air gaps may not be as uniformly planar as structures built with intrinsically more rigid solid dielectrics. This can be a problem if locally depressed areas are formed by bridge layer sag over unsupported air gaps, because the metal filling these depressed areas will remain in the structure after chemical-mechanical polishing (CMP) of the upper levels and be a source of shorts and/or extra and stray capacitance.
Finally, a majority of the prior art methods leave behind a substantial amount of solid dielectric material either under the lines or on the entire via level as a means of providing a mechanical support under the lines to prevent the lines from sagging. However, this increases the capacitance of the structure and diminishes the performance.
In view of the drawbacks mentioned herein above with the prior art processes, there is a continued need for developing a new and improved method in which air gaps can be formed in an interconnect without exhibiting any of the above-mentioned problems.